Chp7:儲存體

Cache
In computer science, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere. If requested data is contained in the cache (cache hit), this request can be served by simply reading the cache, which is comparatively faster. Otherwise (cache miss), the data has to be recomputed or fetched from its original storage location, which is comparatively slower. Hence, the greater the number of requests that can be served from the cache, the faster the overall system performance becomes.

Function

To be cost efficient and to enable an efficient use of data, caches are relatively small. Nevertheless, caches have proven themselves in many areas of computing because access patterns in typical computer applications have locality of reference. References exhibit temporal locality if data is requested again that has been recently requested already. References exhibit spatial locality if data is requested that is physically stored close to data that has been requested already.

Column Address Strobe

 Column Address Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins. In general, the lower the CAS latency, the better.
In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of an arbitrary time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.
 

RAS: Row Address Strobe
Row Address Strobe, one of four control signal types in asynchronous DRAM
Row Address Strobe (RAS) is a signal sent by the processor to a DRAM circuit to tell it that an associated address is a row address. DRAM stores data in a series of rows and columns, and each cell where a data bit is stored has both a row and a column address. A processor uses both RAS and CAS (column address strobe) signals to retrieve data from DRAM. 


 

Chp:7 儲存體

IP
 
Instruction pointer [in′strək·shən ‚pȯint·ər]
(computer science)
A component of a task d
d by the task.
An element of the control component of the stack model of block structure execution, which points to the current instruction.
The EIP register always contains the address of the next instruction to be executed.
You cannot directly access or change the instruction pointer.
However, instructions that control program flow, such as calls, jumps, loops, and interrupts, automatically change the instruction pointer. 

PC

 The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 andItanium microprocessors, and sometimes called the instruction address register (IAR)[1] or just part of the instruction sequencer,[2] is a processor register that indicates where acomputer is in its program sequence.
In most processors, PC is incremented after fetching an instruction, and holds the memory address of (“points to”) the next instruction that would be executed. (In a processor where the incrementation precedes the fetch, PC points to the current instruction being executed.)
Instructions are usually fetched sequentially from memory, but control transfer instructions change the sequence by placing a new value in PC. These include branches (sometimes called jumps), subroutine calls, and returns. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions.
A branch provides that the next instruction is fetched from somewhere else in memory. A subroutine call not only branches but saves the preceding contents of PC somewhere. A return retrieves the saved contents of PC and places it back in PC, resuming sequential execution with the instruction following the subroutine call.

MBR 
A Memory Buffer Register (MBR) is the register in a computer's processor, or central processing unit, CPU, that stores the data being transferred to and from the immediate access store. It acts as a buffer allowing the processor and memory units to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next clock cycle, when it can be either used by the processor or stored in main memory. 

RAM  

Random access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are not random access, as data is read in bursts, although the name DRAM / RAM has stuck. However, many types of SRAM, ROM, OTP, and NOR flash are still random access even in a strict sense. RAM is often associated with volatile types of memory (such as DRAM memory modules), where its stored information is lost if the power is removed. Many other types of non-volatile memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash. The first RAM modules to come into the market were created in 1951 and were sold until the late 1960s and early 1970s.

Other memory devices (magnetic tapes, floppy discs, CDs and DVDs) can access the storage data only in a predetermined order, because of mechanical design limitations.